In semiconductor devices, a heat sink is a passive component that may be arranged to cool the device by dissipating heat away from an active area of the device, such as a p-n junction interface. Heat sinks may commonly be used whenever the inherent heat dissipation ability of the basic semiconductor device is insufficient to control its temperature during operation. This inherent inability to dissipate heat may be present in high-power semiconductor devices such as for example a power transistor manufactured by SOI technology.
SOI technology makes use of a layer of silicon, followed by a layer of insulator material formed on a silicon substrate, in place of conventional silicon substrates used in semiconductor manufacturing, so as to improve device performance. When used in power transistor devices, SOI technology has significant advantages over bulk silicon devices, for example: small area trench isolation; low junction leakage currents; fast reverse recovery behaviour by reducing parasitic device capacitance; increased robustness and the ability to integrate with thyristors and insulated gate bipolar transistors.
A typical individual SOI transistor device 1 is shown in FIG. 1a. In general, such a device may comprise a silicon substrate 10 typically of n-type conductivity, however p-type conductivity silicon substrates are also possible, followed by a oxide layer 12. The oxide layer, known as a buried oxide (or BOX) may be any suitable oxide layer such as silicon dioxide (SiO2). The BOX 12 layer is followed by an SOI layer 14 onto which gate G, source S and drain D contacts are fabricated. Fabrication of such device structures may be achieved by way of the so-called SIMOX process or alternatively by wafer bonding processes.
A high power SOI device 20 as shown in FIGS. 2a and 2b, may typically be formed of an array of pairs of individual SOI transistor devices 1 (of the type illustrated in FIG. 1a or in FIG. 1b discussed further below).
Pairs of individual SOI transistor devices 1 may be arranged as illustrated in FIG. 2c. The pairs of individual SOI devices 1 share a common drain terminal D, with each individual SOI device 1 having its own source S and gate G terminals. In this arrangement the source S and gate G terminals are symmetric about the drain terminal D. For example using the nomenclature of the gate G, source S and drain D reference numerals, this would follow the order S-G-D-G-S.
Typically, there may be a heat sink 16 integrated into the SOI transistor device 1 as shown in FIG. 1b. The heat sink 16 is typically arranged to transfer heat from the active area of the device 1 to the substrate 10. The heat sink may extend from the active region adjacent the source S, through both the SOI layer 14 and the BOX layer 12 to the substrate 10. Typically for every source terminal S (or gate terminal G) there will be a corresponding heat sink 16, as illustrated in FIG. 2c. 
The heat sink may be formed of any appropriate material such as polysilicon, silicon or metal or any suitable material having a lower conductivity than the BOX layer 12. The heat sink may be substantially cuboid rectangular in shape.
In the high power SOI device 20, each individual SOI transistor device 1 is known as a so-called “unit cell” of the high power SOI device 20. As shown in the cross-sectional view of FIG. 2b, the high power device 20 may be formed on a single substrate 10, such as silicon, with a single BOX layer 12 formed on, in the case of wafer bonding, or in the case of SIMOX, in the substrate 10. In this way, the substrate 10 and the BOX layer 12 are common to all individual unit cell SOI transistor devices 1.
As shown in the plan view of FIG. 2a, the high power SOI device 20 also includes an isolation ring 22 extending around the periphery of the high power SOI device 20. Isolation rings are typical for high voltage, high power devices and may be formed as ring of oxide around the device active area to prevent high voltages applied on the device from damaging other low voltage components which may be connected to it. It should be noted, for clarity purposes the heat sinks 16 illustrated in FIGS. 2a and 2b, whilst shown as single heat sinks 16 are pairs of heat sinks, each heat sink 16 of the pair corresponding to an individual unit cell SOI transistor devices 1.
In generally, problems surrounding poor heat dissipation in high power SOI devices may be more significant than in bulk silicon devices having a BOX layer, because the BOX layer may have a lower thermal conductance, typically only 1% of the thermal conductance of that of comparable bulk silicon devices.
FIG. 5a shows two-dimensional device surface temperature simulations (where the temperature is shown in Kelvin) of a typical high power SOI device of the type shown in FIGS. 2a to 2c. The temperatures are taken from the centre (shown as the origin of the x-axis (Ldev/2) and the y-axis (Wdev/2)) to respective adjacent edges of the high power SOI device 20 operating at a power of 5.2 watts. As can be seen from FIG. 5b, which shows a one dimensional temperature profile along the x-axis, the temperature peaks to a maximum at the centre of the high power SOI device and then falls away for each SOI device 1 from the centre taken along the x axis towards the edge (that is, the isolation ring 22) of the high power SOI device 20.
Simulations show that during operation, the high power SOI device 20 may exhibit a non-uniform temperature distribution for different unit cells or different regions of unit cells making up the high power SOI device 20. Looking at FIGS. 5a and 5b, due to heat dissipation issues mentioned above, the highest operating temperature peak is concentrated at the central region of the high power SOI device 20 gradually reducing to lower operating temperature at the edge of the high power SOI device 20. This temperature peak is due to the inability to dissipate heat from the central area of the device due to the conductance issues associated with SOI devices having BOX layers.
The temperature peak (also called a hot spot) which may be generated in the centre of the high power SOI device 20 during operation is the weakest point for device reliability which can result in breakdown of one or more SOI devices 1 at or near the hot spot. The result of device breakdown is that the SOI power device 20 may fail completely, or alternatively breakdown of an individual SOI device may reduce the functionality of the overall high power SOI device.
Referring again to FIG. 1b and FIGS. 2a and 2b, it is known to integrate a heat sink 16 into an SOI device 1. The heat sink 16 acts to conduct heat from the SOI layer 14 through the BOX layer 12 to the substrate. Such an SOI device 1 comprising such a heat sink 16 may form part of the larger scale high power SOI device 20 of the type discussed above (and illustrated in FIGS. 2a and 2b). However, adding heat sinks 16 for each individual SOI device 1 making up the high power SOI device 20 in this way may also consume a large amount of device area and the larger the device area the higher the on-state resistance (Rdson) of the high power SOI device 20 will be.
The present invention seeks to provide a semiconductor device which mitigates or overcomes at least one of the above mentioned problems.